1. Field of the Invention
This invention relates to a technique of driving a plasma display panel, and more particularly to a sustain driving apparatus and method for a plasma display panel that is adaptive for reducing power consumption as well as stabilizing a driving waveform.
2. Description of the Related Art
Generally, a plasma display panel (PDP) is a picture display device using a gas discharge, and is advantageous to a large screen. The PDP has provided an enhanced picture quality owing to the recent improvement of circuit technique and panel structure.
Recently, there has been developed various flat panel devices that are capable of reducing a heavy weight and a large bulk, which are drawbacks of the cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence display (ELD), etc.
The PDP of these flat panel display devices allow an ultraviolet ray generated upon discharge of an inactive mixture gas, such as He+Xe, Ne+Xe or He+Xe+Ne, etc., to radiate a phosphorous material to thereby display a picture. The PDP has been used for a high-resolution television, a monitor and an internal or external advertising display because it has a rapid response speed and is suitable for displaying a large-area picture.
The PDP is largely classified into an alternating current (AC) type in which electrodes are covered with a dielectric material and a discharge is caused with the aid of wall charges accumulated onto the dielectric material, and a direct current (DC) type in which a discharge is caused between electrodes opposed in the longitudinal direction. The AC-type PDP employs a surface discharge occurring at the surface of the dielectric material with which the electrodes are coated. A sustaining pulse for sustaining a cell discharge of the AC-type PDP has a high voltage of hundreds of volts (V) and a frequency of hundreds of KHz.
When the sustaining pulse is applied to the PDP for the purpose of causing a charge/discharge, a capacitive load of the panel does not cause an energy waste, but a lot of energy loss occurs at the PDP because a direct current (DC) power source is used to generate a sustaining pulse. Particularly, if an excessive current flows in the cell upon discharge, then an energy loss is increased. In order to recover an energy generated unnecessarily within the panel, that is, a reactive power, a driving circuit of the PDP includes an energy recovering circuit.
Referring to FIG. 1, a conventional energy recovering circuit of the PDP includes first and third switches S11 and S13 connected, in parallel, between an inductor L and an external capacitor Cs, a second switch S12 for applying a sustain voltage Vs to a panel capacitor Cp, and a fourth switch S14 for applying a ground voltage GND to the panel capacitor Cp.
First and second diodes D11 and D12 for limiting a reverse current are connected between the first and third switches S11 and S13. The panel capacitor Cp is an equivalent expression of a capacitance value of the panel.
FIG. 2 is a timing diagram and a waveform diagram representing an ON/OFF timing of switches shown in FIG. 1 and an output waveform of the panel capacitor shown in FIG. 1.
An operation of the energy recovering circuit shown in FIG. 1 will be described in conjunction with FIG. 2.
First, prior to a time t1, it is assumed that a voltage charged in the panel capacitor Cp should be 0 volt and a voltage equal to Vs/2 should be charged in the external capacitor Cs.
At a time t1, the first switch S11 is turned on and keeps the ON state. Then, a voltage stored in the external capacitor Cs is applied, via the first switch S11 and the first diode D11, to the inductor L. At this time, the inductor L constructs a serial LC resonance circuit along with the panel capacitor Cp. Accordingly, the panel capacitor Cp begins to be charged into a resonant waveform by a resonant waveform applied, via the inductor L, to the panel capacitor Cp, and is charged until a sustaining potential Vs.
At a time t2, the first switch Sw1 is turned off and is kept in the OFF state while the second switch S12 is turned on and is kept in the OFF state. Then, a sustaining voltage Vs from the sustaining voltage source Vs is applied, via the second switch S12, to the panel capacitor Cp. Accordingly, a voltage of the panel capacitor Cp remains at a sustaining level Vs at the t2 time.
At a time t3, the second switch S12 is turned off and is kept in the OFF state while the third switch S13 is turned on and is kept in the ON state. Then, a voltage of the panel capacitor Cp is recovered into the external capacitor Cs by way of the inductor L, the second diode D12 and the third switch S13.
At a time t4, the third switch S13 is turned off and is kept in the OFF state while the fourth switch Sw4 is turned on and is kept in the ON state. Accordingly, a ground voltage GND is applied to the panel capacitor Cp to maintain the panel capacitor Cp at the ground voltage GND.
The conventional energy recovering circuit shown in FIG. 1 has a disadvantage in that it requires a high voltage source Vs of hundreds of volts so as to maintain the panel at the sustain level, thereby increasing power consumption of the driving circuit. Furthermore, the energy recovering circuit of FIG. 1 has a disadvantage in that it has a high cost because switching devices having a high voltage-resisting property are used as the switches S11 to S14 implemented by a semiconductor device such as a field effect transistor (FET) such as it can provide a stable operation at a high voltage.
In order to overcome the above problems of the energy recovering circuit of the PDP, there has been suggested a low-voltage driving energy recovering apparatus in which a voltage equal to ½ of the sustaining voltage is used for a driving voltage source.
Referring to FIG. 3, the low-voltage driving energy recovering apparatus includes a first switch S21 connected to an ½ sustaining voltage source Vs/2, an external capacitor Cs between the first switch S21 and a ground voltage source GND, a second switch S22 connected between a first node N1 provided between the first switch S21 and the external capacitor Cs and the inductor L, and a third switch S23 connected between a second node N2 provided between the inductor L and a panel capacitor Cp and the ground voltage source GND.
Herein, the panel capacitor Cp is an equivalent expression of a capacitance value of the PDP.
An operation of the low-voltage driving energy recovering apparatus will be described in conjunction with FIG. 4 below. In FIG. 4, a waveform Vn2 represents a voltage of the second node N2 that is an output node.
At a time T1, the first and third switches S21 and S23 keep an ON state while the second switch S22 keeps an OFF state. Accordingly, at a time T21, the external capacitor Cs charges a voltage into Vs/2, and the panel capacitor Cp maintains a ground voltage GND.
At a time T2, the first and third switches S21 and S23 are turned off while the second switch S22 is turned on. Accordingly, at a time T2, the panel capacitor Cp constructs a serial resonance circuit along with the inductor L to charge a voltage passing through the inductor L until the sustain level Vs.
Such a low-voltage driving energy recovering apparatus has an advantage in that it can reduce a driving voltage to ½ in comparison with the energy recovering circuit shown in FIG. 1 and reduce switching devices to three. However, the low-voltage driving energy recovering apparatus has problems in that it fails to constantly keep a potential of the discharge voltage capable of causing a stable discharge because a driving voltage is generated only by the resonant waveform and it fails to provide a stable driving waveform because a frequency of the resonant waveform is changed depending upon a load variation in the panel capacitor Cp.